1. Field of the Invention
The present invention relates to electron beam lithography. More particularly, the present invention relates to a multilayer resist material for use in an electron beam lithographic process and a method for the formation of a resist pattern on a substrate or base material such as a metal or semiconductor by using said multilayer resist material. Since the resist material used does not cause charging up or electrification therein during electron beam exposure and such charging up is not induced even if a thickness of the lowermost pattern-receiving layer thereof is increased, and further, the resulting resist pattern exhibits a very high resistance to dry etching, the present invention can be widely utilized, with satisfactory results, in the production of semiconductor devices and similar devices which require a high resolution processing on the order of submicrons, for example, integrated circuits, large-scale integrated circuits, and bubble memory devices.
2. Description of the Related Art
In the production of semiconductor devices and the like, electron beam lithography is frequently used in combination with a multilayer resist process to obtain a high quality and very fine resist pattern having a high resistance to dry etching, such as reactive ion etching, plasma etching or sputter etching, used for a selective etching of the underlying substrate. Typical of these multilayer resist processes are a two-layer resist process and a three-layer resist process.
Generally, the resist material used in the two-layer resist process consists of a thinner upper resist layer sensitive to an electron beam and a thicker lower resist layer, also referred to as a leveling layer because it can effectively level an uneven surface of the underlying substrate, and is highly resistant to dry etching. As an example of this two-layer resist process, a novolak resist such as an "OFPR"-series resist commercially available from Tokyo Oka Co., Ltd., is coated on a selected substrate to form a lower resist layer. To avoid dissolution thereof, the lower resist layer is conventionally insolubilized by a thermal treatment at an elevated temperature of about 200.degree. C. After the insolubilization step, a silicone resist such as silylated polymethylsilsesquioxane (PMSS) is coated on the lower resist layer to form an upper resist layer. The resultant two-layer resist material, is then patterned by electron beam exposure and developed, and a patterned upper resist is thus obtained. Thereafter, the lower resist layer is dry etched by oxygen plasma, for example, through the patterned upper resist which acts as a mask, and the pattern of the upper resist is thus transferred to the underlying resist layer. The resulting resist pattern in the lower resist layer should have higher accuracy and larger thickness, namely, a higher aspect ratio. The term "aspect ratio", as generally recognized in the art, means the ratio of the layer thickness to the pattern width of the resist pattern. A higher aspect ratio indicates that the resist pattern has a high dimensional accuracy.
The two-layer resist process described above is characterized in that the two essential functions of the resist, i.e., formation of fine resist patterns with a high accuracy and leveling of the unevenness of the underlying substrate, rely separately upon upper and lower resist layers which are essentially different from each other. Similarly, although not described herein in detail, the three-layer resist process has been used in the production of semiconductor and other devices on the same grounds. An interlayer to be inserted between the upper resist layer and the lower resist layer is generally used to assist the function of the upper and/or lower layers, if not satisfactory.
The multilayer resist process is generally considered to be one of the most useful resist processes, but suffers from a serious problem of a charging up or electrification of the resist used. This problem occurs during electron beam exposure of the upper resist layer. Namely, when the upper resist layer is irradiated as a pattern with an electron beam, charges of the irradiated electron beam tend to remain in the underlying resist layer such as the novolak resist layer. If these remaining charges are at a high level or are increased, when a subsequent electron beam exposure is carried out on the same resist layer, the irradiated electron beam is bent or curved as a result of the action of a repulsion force of those remaining charges on the resist layer. This incorrect irradiation of the electron beam results in defects such as an incomplete detection of the alignment marks, erroneous registration of the alignment marks, and shifting of the electron beam patterns, thereby causing a notable reduction of the pattern accuracy in the resulting resist patterns.
Several methods of preventing charging up in the resist layer during electron beam exposure have been disclosed. For example, it is disclosed in "Kenkyu Jitsuyoka Hokoku Research and Practice Report", Vol. 33, No. 4, p. 655-663, 1984, published by Nippon Telegraph and Telephone Public Corporation, that the formation of a Mo (molybdenum)-deposited layer on an underlying resist layer will effectively prevent such charging up. As illustrated in FIG. 1, this disclosure teaches a four-layer resist (CMS/Mo/SiO.sub.2 /AZ) which essentially consists of a semi-electrically insulating GaAs substrate 1 having applied thereon, in sequence, a CVD (chemical vapour deposition)-deposited silicon nitride layer 2, a lower resist layer 3 such as AZ 1470 commercially available from Hoechst AG, a silicon oxide layer 4, a molybdenum layer 5, and an upper resist layer 6 such as CMS (chloromethylated polystyrene). This four-layer resist can prevent charging up during electron beam patterning, and thus can prevent an erroneous alignment of patterns, in comparison with the single CMS resist.
Further, it is disclosed in N. Katoh et al.: "Application of .phi.-MAC Two-Layer Resist in GaAs IC", Autumn Symposium Preprint, 12p-T-12, Japan Society of Applied Physics, 1984, that a deposition of metals such as Al (aluminum) onto a resist layer effectively prevents charging up in the resist layer. The resist layer used herein is a duplitized resist layer of phenylmethacrylate-methacrylic acid copolymer (.phi.-MAC), in view of the formation of undercuts for the lift-off process. In the methods of this and the above-cited literature, the metal deposition layer such as Mo and Al has an electrical conductivity, and therefore, can prevent an electrification of the underlying resist layer. Nevertheless, these methods complicate the production process, due to the deposition of metals, and make the detection of alignment marks more difficult due to a reduced transmission of electrons caused by the presence of the deposited metal layer.
In 1986, Y. Takasu et al. disclosed in "Three-Layer Resist Process Using a Coated Conductive Layer as an Interlayer", spring Synposium Preprint, 1p-Z-13, Japan Society of Applied Physics, 1986, that use of an ITO (indium-tin oxide) layer in place of the SOG (spin-on-glass) interlayer in the three-layer resist process can prevent a reduction of the pattern accuracy due to charging up of the resist. As shown in FIG. 2, in this improved method, a silicon substrate 1 has formed thereon, in sequence, a lower resist layer 7 such as OFPR-800 commercially available from Tokyo Oka Co., Ltd., an ITO interlayer 8 and an upper resist layer 9 such as PMMA (polymethylmethacrylate) or OFPR-800. The ITO interlayer 8 can be easily formed by coating, and an electrical insulating property thereof can be converted to an electrical conductivity by a thermal treatment at a temperature of 280.degree. C. or more.
At the same Spring Symposium, M. Kakuti et al. disclosed a two-layer resist process using an electrically conductive carbon resist as a lower resist layer (see, Preprint 1p-Z-10). As shown in FIG. 3, the resist material is formed on a substrate 1 such as quartz and essentially consists of a lower resist layer 10 of plasma CVD carbon and an upper resist layer 11 such as SNR (silicone-type negative-working resist). Since the lower resist layer 10 has an electrical conductivity, this two-layer resist process ensures the conduction of an electron beam exposure on the insulating substrate without charging up the resist layer.
Nevertheless, use of conductive layers such as ITO and CVD carbon requires treatments of such layers at an elevated temperature such as 280.degree. C. or more (for ITO) and 250.degree. to 400.degree. C. (for CVD carbon), and thus has a danger that the underlying substrate will be destroyed. Moreover, as in the use of metal layers as a conductive layer described in the previous paragraphs, the use of a conductive layer is also complicated, due to constitution of the resist used. Since none of the prior art multilayer resist processes completely solves the problem of charging up in the resist layer during the electron beam exposure, there is still a need to provide an improved multilayer resist material and pattern formation method.
As described in detail hereinafter, the present inventors found that the use of particular polymers or copolymers of haloalkylated aromatic vinyl compound as the lowermost layer of the multilayer resist material in an electron beam lithographic process can solve the problems of the prior art methods, including charging up. None of the prior arts discloses or teaches this use and the superior effects thereof. For example, Japanese Unexamined Patent Publication (Kokai) No. 60-257522 teaches a three-layer resist material which, as shown in FIG. 4, consists essentially of a lower resist layer 12, formed on a semiconductor substrate 1, such as negative-working resist, for example, CPMS (chlorinated polymethylstyrene), an interlayer 13 such as Ti (titanium), and an upper resist layer 14 of electron beam-sensitive resist such as polystyrene. Although this application teaches the use of CPMS, the object thereof is not directed to a prevention of charging up of the resist layer during electron beam exposure, in that the object of this application is to prevent cracking caused due to pinholes in the interlayer 13. As disclosed on page 2, left lower column, of referenced application, cracks in the interlayer 13 can be prevented if the interlayer 13 and the upper layer 14 are sequentially formed after gelation of the lower layer 12. Further, according to the method of this application, after coating the lower layer 12 and before formation of the interlayer 13, it is essential to subject the coated layer 12 to a series of steps of prebaking at a predetermined temperature and time, overall exposure of for ultraviolet rays, development of the exposed layer, and a two-step postbake (first postbake and second postbake).
Before inventing the present invention, the inventors found an improved pattern forming method which does not cause a problem of charging up and filed a patent application in Japan on Aug. 27, 1986 under Japanese Patent Application No. 61-199116 (see, Japanese Unexamined Patent Publication (Kokai) No. 63-56655 published on Mar. 11, 1988). The pattern forming method is characterized by coating a negative-working resist consisting of an aromatic vinyl compound polymer which vinyl radical may be partially substituted with halogen on a substrate and irradiating the resist coating with far UV-rays, charged particle rays or X-rays to form a lower layer of the multilayer resist process. However, at that stage, they could not find a combined effect of the molecular weight and haloalkylation degree of polymers or copolymers of haloalkylated aromatic vinyl compound in preventing the charging up during electron beam exposure, and other effects of the present invention.